How to handle power interrupts and irregular power losts of FN990 devices?

The main question is what will happen if the power voltage is irregularly switched off. Okay, the mobile connection will be lost, but what about the device itself? Can it be powered on, and will the device work fine after the Initialization process and network registration? Or must damage be avoided? Is it necessary to shut down the device fast (in ~50 ms) or in regular mode before the power can be switched off or a power interruption occurs?
This would influence the power stage of the whole device due to the need buffering voltage for a defined shutdown. Does anyone have experience in this topic?
What is the best practice? Are there any documents besides the hardware guide where this topic has been discussed?

1. The question is what will happen if the power voltage is irregularly switched off. Okay, the mobile connection will be lost, but what about the device itself?
[Answer]

In the event of an unwanted power supply loss, FN990 module device can be switched off without any risk of filesystem data corruption by implementing the Fast Power Down feature. The Fast Power Down feature permits to reduction current consumption and the time-to power off to a minimum.

2.Can it be powered on, and will the device work fine after the Initialization process and network registration?
[Answer]

Yes, the module can be powered on and work fine again, if power voltage back to valid operating range 3.135 V - 4.4 V;

3.Or must damage be avoided? Is it necessary to shut down the device fast (in ~50 ms) or in regular mode before the power can be switched off or a power interruption occurs?

[Answer]

“Damage must be avoided through proper shutdown procedures.”

For controlled power-off scenarios: It is mandatory to perform either:

  • Graceful Shutdown (~8 seconds, via FULL_CARD_POWER_OFF_N asserted low), or

  • Fast Shutdown (~45ms, via GPIO trigger)

For unwanted power interruption and irregular power loss: The FN990 includes internal protection, but repeated improper shutdown may damage the device and void warranty (Refer to Hardware design guide’s Section 7.2.2.2 Warning). To handle such scenarios, the host system should implement:

1). Power-fail detection circuit to trigger Fast Shutdown when VPH_PWR drops below threshold

2).Hold-up capacitor on VPH_PWR line to provide sufficient energy for the ~45ms Fast Shutdown completion

The hardware design guide document explicitly warns: “Failure to follow recommended shut-down procedures might damage the device and consequently void the warranty.”

The hardware design guide document emphasizes that a quick shutdown requires VPH_PWR to remain at a high level; otherwise, the module will restart (Section 7.2.2.2 Note). Therefore, the design of the buffer capacitor is crucial.

4.This would influence the power stage of the whole device due to the need buffering voltage for a defined shutdown.
Does anyone have experience in this topic?
What is the best practice?
Are there any documents besides the hardware guide where this topic has been discussed?

[Answer]

Based on Section 5 Power Supply and Section 10.2 of the document, the following best practice recommendations are provided:

1). Hold-up Capacitor Design (for Unexpected Power Loss)

Parameter Recommended Value Document Reference
Main hold-up capacitor 100μF tantalum capacitor Table 15, Section 5.3.1.1
ESR requirement Low ESR (<100mΩ) Section 5.3.1.1
Voltage rating ≥10V Section 5.3.1.1
Peak current support 4A @ 3.3V Table 15

Calculation formula (hold-up time estimation):

  • Typical consumption (standby): <5mA → 100μF can support extended duration

  • Typical consumption (operating): 350mA-2000mA → specific hold-up time calculation required

thold​=IC×ΔV​=0.5A100μF×0.5V​≈100ms

This is sufficient to cover the Fast Shutdown requirement of ~45ms.

2). Recommended Power Architecture

External Power Supply (3.3V-4.2V)

├── Protection Diode (reverse polarity) ──┐
│ │
├── 100μF Tantalum Capacitor (hold-up) ──┤
│ │
├── Power-fail Detection Circuit ────────┤
│ (Undervoltage monitoring, triggers GPIO) │
│ │
└── VPH_PWR ────── ─────────────┘
(Pins 2,4,70,72,74)

3). Critical Design Points

Design Item Specific Requirement Document Section
PCB trace width Sufficient to support 4A peak current Section 5.3.3
Capacitor placement Close to module power input pins or close to inductor Section 5.3.3
Thermal design Large bottom solder pad + TIM + heatsink Section 5.3.2, 3.8.1
ESD protection ±4kV for antenna ports, ±1kV for other ports Section 10.2.1

4). Power-fail Detection Circuit Recommendation

VPH_PWR ──┬── Resistor Divider ──┬── Comparator/GPIO ──→ FN990 (Fast Shutdown Trigger)
│ │
GND Reference Voltage (e.g., 3.0V)

Trigger Fast Shutdown when VPH_PWR < 3.0V

5). Additional Reference Documents

Per Section 14 Related Documents, the following documents are recommended:

Document Number Title Relevant Content
1WV0301804 FN990 Thermal Design Guide Thermal design and power management
1W0301750 FN990 SW User Guide Fast Shutdown AT command configuration
80691ST11097A FN990 AT Commands Reference Guide AT#SHDNIND shutdown indicator configuration

If you have further questions, please send mail to TS-EMEA@telit.com / TS-AMERICAS@telit.com to create ticket, there will be dedicate FN990 professional technical team to support you.